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Smart Interconnects

The goal of this activity was to provide a comprehensive study of a smart interconnect concept, in the context of the AO application, including hardware, firmware, middleware and development environment considerations.

This development was done using an integrated FPGA development environment (QuickPlay), supporting 10G TCP/UDP and PCIe gen 3, and hosting various features including protocol handling, data processing and pear-to-pear access on the PCIe bus and including the support for about 10 various FPGA boards including µXComp from Microgate.

Two designs were implemented :

  • Smart interconnect design
  • FakeCam/FakeDMC design

The RTC design supports UDP communication and a number of DMA engines enabling peer-to-peer communication between the µXComp and the GPUs. On top of this encapsulation/decapsulation features are also present as well as latency measurement. A typical design is shown below.