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Real-time HPC using accelerators and smart interconnects

We propose, in this axis of development, to demonstrate the scalability of accelerator based solutions for real-time HPC data-intensive applications. The primary objective of this axis of development is to prototype a cluster, able to reach a sustained performance of 1.5 TMAC/s of computing power and processing 250 Gb/s of streaming data with a maximum jitter of 100 ┬Ás over 1s of operation and using commodity accelerators such as GPUs as compute engines. (obj. 1.1)

One objective of this axis of development is to provide a COTS NIC solution, based on the FPGA technology, with smart features, compatible with existing high performance switch solutions, based on standard serial protocols (TCP/UDP through 10G Ethernet and 40G Infiniband), and supported in mainstream non proprietary middleware. (obj. 1.2)

Another objective of this axis of development is to complement the ecosystem of an existing integrated FPGA development environment (QuickPlay from PLDA), by providing data handling and computational blocks tailored to our application, and support for several FPGA options and board designs. The end user API will be made interoperable with mainstream non proprietary middleware. (obj. 1.3)

The last objective of this axis of development is to assess the performance of Cholesky factorization on the prototype cluster, as well as the overall control matrix computation algorithm and the control matrix upload to the controller with minimal introduced latency and jitter in the control process. (obj. 1.4)

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